1. Field of the Invention
The present invention relates to a method for driving a plasma display including cells defined at intersections of a plurality of electrodes.
2. Description of the Background Art
FIG. 11 shows an overview of a configuration of a background-art plasma display such as disclosed in Japanese Patent Application Laid Open Gazette 7-160218. This figure shows a display panel 101, sustain electrodes X serving as the first electrodes and scan electrodes Y1 to Yn serving as the second electrodes which are disposed in parallel on a glass substrate serving as the first substrate and address electrodes A1 to Am serving as the third electrodes arranged on a glass substrate serving as the second substrate opposed to the above-mentioned glass substrate in a direction perpendicular to the sustain electrodes X and the scan electrodes Y1 to Yn.
The plasma display has n.times.m pixels, that is i=1 to n and j=1 to m, and a discharge cell is defined at an intersection between a given scan electrode Yi and a given address electrode Aj. The scan electrodes Y1 to Yn and the address electrodes A1 to Am are insulated from and independent of one another so as to be independently driven to perform address selection for each of the defined discharge cells to turn on/off.
The sustain electrodes X are paired with the scan electrodes Y1 to Yn respectively and respective one ends of the sustain electrodes X are connected in common. The first to fourth voltages to be applied to these electrodes as pulses are generated by a power supply circuit 102 and then supplied for the electrodes through a Y common driver 103, a scan driver 104, an X common driver 105 and an address driver 106. The Y common driver 103, the scan driver 104, the X common driver 105 and the address driver 106 are controlled by a control signal from a control circuit 107. The control circuit 107 generates the control signal based on externally-supplied display data DATA, a dot clock CLK, a vertical synchronizing signal VSYNC and a horizontal synchronizing signal HSYNC in synchronization with the display data.
FIG. 12 is a cross-sectional illustration showing a structure of a cell in the plasma display panel. This figure shows the sustain electrode X and the scan electrode Yi both of which are formed on a glass substrate 108 extending in a direction perpendicular to this paper, a dielectric layer 109 for holding wall charges formed on the sustain electrode X and the scan electrode Yi, a protective layer 110 formed on a surface of the dielectric layer 109, the address electrode Aj formed on a glass substrate 111 opposed to the glass substrate 108, extending in a side-to-side direction of this paper, a phosphor 112 formed on the address electrode Aj, a barrier rib 113 formed on a pixel boundary and a discharge space 114 between the protective layer 110 and the phosphor 112, being filled with, for example, Penning mixed gas of Ne and Xe.
Now, an operation will be discussed.
FIG. 13 is an illustration of applied voltage waveforms for showing a background-art method for driving a plasma display, with a resetting step, a writing step and a discharge sustaining step in time series. In this figure, prior to the writing step, a priming pulse 121 is applied as a pulse of the first voltage between the sustain electrode X and the scan electrode Yi in the resetting step, to cause a discharge between the sustain electrode X and the scan electrode Yi, producing space charges in the discharge space 114, and to cause a self-erase discharge on a fall of the priming pulse 121, bringing a state of charges in the cell into a charge-erased state (where accumulated charges in the dielectric layer 109 on the sustain electrode X and the scan electrode Yi become zero). Subsequently, in the writing step, a scan pulse 122 is applied to the scan electrodes Y1 to Yn in sequence and an address pulse is applied to the address electrodes A1 to Am in accordance with the display data, to generate the second voltage across the address electrodes A1 to Am and the scan electrodes Y1 to Yn, causing a writing discharge. After that, in the discharge sustaining step, a sustain pulse is applied alternately to the sustain electrode X and the scan electrode Yi as the fourth voltage, to sustain the discharge.
The first voltage refers to a potential difference across the sustain electrode X and the scan electrode Yi. In FIG. 13, assuming that the potential of the scan electrode Yi is zero, a pulse of potential Vp is applied to the sustain electrode X and therefore Vp is the first voltage. Alternatively, for example, a pulse of potential Vp.alpha. and a pulse of negative potential Vp.beta. (where the first voltage=Vp.alpha.-Vp.beta.) may be applied to the sustain electrode X and the scan electrode Yi, respectively, as discussed later.
Similarly, the second voltage refers to a potential difference across the address electrode Aj and the scan electrode Yi (in FIG. 13, Va-Vsp is the second voltage, and since Vsp is a negative potential, the expression, .vertline.Va.vertline.+.vertline.Vsp.vertline. is the second voltage, may be made). The fourth voltage refers to a potential difference between the sustain electrode X and the scan electrode Yi (in FIG. 13, Vs is the fourth voltage). Thus, a display operation is achieved through repeating the resetting step, the writing step and the discharge sustaining step in sequence.
Next, with reference to FIGS. 14(a0) to 14(f0), discussion will be made on state changes inside a cell in the resetting step. FIGS. 14(a0) to 14(f0) correspond to time periods (a) to (f) of FIG. 13, respectively. After the end of the preceding driving cycle, in respective portions corresponding to the sustain electrode X and the scan electrode Yi which are adjacent to each other, a certain amount of wall charges of reverse polarities are accumulated (FIG. 14(a0)). In this state, when the priming pulse 121 is applied across the sustain electrode X and the scan electrode Yi, a discharge occurs across the sustain electrode X and the scan electrode Yi (FIG. 14(b0)). Electrons and positive ions generated by the discharge are attracted towards the reversely-polarized sustain electrode X and scan electrode Yi respectively and accumulated on a surface of the dielectric layer 109 to act as respective wall charges on the sustain electrode X and the scan electrode Yi. Since these wall charges reduce the electric field strength in the discharge space, the discharge immediately converges to a termination (FIG. 14(c0)).
When the application of the priming pulse 121 to the sustain electrode X and the scan electrode Yi is stopped, a discharge occurs across the sustain electrode X and the scan electrode Yi by the wall charges (FIG. 14(d0)). Then, the positive ions and the electrons recombine together, to reduce the wall charges (FIG. 14(e0)). At this time, the wall charges ideally become zero, but in some cases, some of the wall charges actually remain as residual wall charges (FIG. 14(f0)).
In the resetting step, the priming pulse 121 (full write pulse) applied across the sustain electrode X and the scan electrode Yi performs the following functions;
a. to once forcefully cause a discharge, regardless of the previous display state, resetting the state of the charges into a relatively uniform state, PA1 b. to generate space charges for easy subsequent discharges, and PA1 c. to perform an erase operation (to return all the discharge cells into an erased state, that is, a state of no accumulated charge). PA1 (1) causing a dielectric breakdown inside the plasma display panel, PA1 (2) raising cost due to the necessity for increasing a breakdown voltage of a driver circuit, and PA1 (3) enhancing background luminance (luminance in black display) due to the priming discharge and lowering the contrast ratio.
With the above configuration of the background-art plasma display, all the wall charges are not necessarily erased by the self-erase discharge and some residual wall charges are left in some cases. Until now, it has been believed that it is no problem if the residual wall charges cause no false discharge in a cell of no writing, in other words, cause no erase failure in terms of quantity.
It is found, however, that the residual wall charges disadvantageously cause a problem of suppressing the priming discharge in the next driving cycle as well as causing the erase failure. The problem will be discussed with reference to FIGS. 14(a1) to 14(b1). When the cell in which the residual wall charges are left is a cell of no writing (off-cell), there is no chance to cause a discharge during writing and sustaining (FIG. 14(a1)). Therefore, when the priming pulse 121 is applied in the next cycle, the wall voltage by the residual wall charges offsets the externally-applied priming pulse voltage, and when a relation as EQU (externally-applied voltage)-(wall voltage by residual charges)&lt;(firing voltage of the cell)
is hold, no priming discharge occurs (FIG. 14(b1)).
If no discharge occurs when the priming pulse is applied, the priming pulse 121 does not accomplish its function, not leading to the next writing and sustaining discharge, and further no discharge occurs when the next priming pulse is applied, which is a vicious circle, resulting in a display failure.
The amount of residual charges depends on variation in discharge characteristics of the cell and stochastic fluctuation in intensity of the discharge, and these problems arise when the quantity of the residual charges are neither large nor small. Specifically, when small in quantity, a normal discharge occurs when the next priming pulse is applied. When large in quantity, though a false discharge occurs in writing or sustaining to cause an extra emission momentarily, a discharge occurs by applying the priming pulse in the next driving cycle, to reset the charges into a normal state.
With reference to FIG. 15, discussion will be made on the range of the wall voltage to cause an operation failure.
The vertical axis is a value of the wall voltage by the residual wall charges, and it is defined that the positive polarity (upward along the axis) represents a case where positive and negative residual wall charges are accumulated on a Y-electrode and an X-electrode, respectively, and the negative polarity (downward along the axis) represents a case where negative and positive residual wall charges are accumulated on the Y-electrode and the X-electrode, respectively. Therefore, the wall voltage of positive polarity means that the wall voltage is superimposed to aid the priming pulse 121.
Further, the voltage Vf is a firing voltage of the discharge space, and when the sum of the wall voltage and externally-applied voltage exceeds Vf, a discharge occurs. When the value of the residual wall charges is in a range that the voltage does not exceed the absolute value of Vf even if the priming pulse 121 is applied or the sustain pulse is applied, an operation failure may occur. To surely cause the full write discharge even if the residual wall discharges are left in such an amount, it is necessary to apply such a high priming pulse voltage as to offset the wall voltage by the residual charges and then exceed the firing voltage.
When the high priming pulse voltage is applied, however, there arises new problems of;
Though a model in which the residual wall charges are left due to the self-erase discharge on the fall of the priming pulse is discussed, other than that, there are problems of possibility of causing the same state of charges as above by incomplete writing and/or sustaining discharge, where priming discharge no longer occurs, and the like.
Another problem is difficulty in increasing luminous efficiency. There are some methods to increase luminous efficiency, and among them is to widen a space between the sustain electrode and the scan electrode. It is reported in, for example, "ASIA DISPLAY '95, Evaluations of Discharge Cell Structure for Color AC Plasma Display Panels" by T. Akiyama, M. Umeoka, that widening the space allows an increase in luminous efficiency. When the space between the sustain electrode and the scan electrode becomes wider, however, the firing voltage Vf rises at the same time and higher voltage is needed to drive. That results in a hard driving. The rise in firing voltage causes not only the rise in sustain voltage but also the rise in priming voltage.
The rise in priming voltage will be discussed with reference to FIGS. 16(a) to 16(c), 17 and 18. A voltage required as the priming voltage is indicated by a line of FIG. 16(a). In a region over the line, a good priming operation can be performed. This region is a synthesis of respective two regions defined over the lines of FIGS. 16(b) and 16(c). The line of FIG. 16(b) is expressed as Vs+Vp=2.times.Vf. The region over the line, where it is possible to invert the residual wall charges by the sustain pulse 123 and the priming pulse 121, corresponds to a range of the sustain voltage Vs and the priming voltage Vp to eliminate "the range to cause an operation failure".
FIG. 16(c) shows a line where Vp is constant regardless of Vs (Vp-a=Vf: a is a constant), and in the region over the line, it is possible to cause a self-erase discharge on the fall of the priming pulse 121. Specifically, (Vp-a) indicates a value of the wall voltage by the wall charges accumulated on the rise of the priming pulse 121 and it is shown that the self-erase discharge occurs when this voltage exceeds the firing voltage. In a normal range of sustain voltage, whether the residual charges can be inverted or not mainly determines the minimum priming voltage.
It is assumed here that when the space between the electrodes is widened from g1 to g2 (g2&gt;g1), the firing voltage changes from Vf1 to Vf2 (where Vf2&gt;Vf1 and Vf2-Vf1=.DELTA.Vf). Then, as shown in FIG. 17, the priming voltage required to invert the residual charges rises by 2.times..DELTA.Vf. Explanation for this is that with changes from +Vf1 to +Vf2 and from -Vf1 to -Vf2 as shown in FIG. 18, the required priming voltage changes from Vp1 to Vp1+2.noteq..DELTA.Vf, rising by 2.times..DELTA.Vf. Thus, when the firing voltage rises by .DELTA.Vf, the priming voltage rises by (2.times..DELTA.Vf), which is twice as large as the rise of the firing voltage, and therefore driving becomes harder.
For the above reason, conventionally, the space between the electrodes is determined near a value to make the firing voltage minimum, i.e., the minimum value of a curve known as Paschen's curve. Another well-known method for increasing luminous efficiency is to lower the intensity of one discharge and to increase the repeat number of discharges. In a pulse memory system of a DC plasma display, short pulses are applied in sequence in high repeat number.
In an AC plasma display, however, since the intensity of the discharge by one pulse depends on the panel structure and the applied voltage and the applied voltage is limited in a range of voltage which enables discharge sustaining, it is difficult to lower the luminous intensity. Moreover, since the discharge occurs only near the rise of the sustain pulse (see FIG. 19), it is necessary to increase the frequency of the sustain pulse in order to increase the repeat number of discharge. Then, it becomes impossible to ensure the duration (i.e., width) of the sustain pulse large enough to fully stabilize the wall charges, and that raises a problem of unstable operation.